An on-line fault detection technique based on embedded debug features

An increasing number of applications require being able to detect possible faults arising during the normal activity of the electronic system: for this reason, on-line fault detection is a hot topic today. This paper proposes a new technique which is suitable for microprocessor-based systems (no matter whether they are implemented in a single device or with discrete COTS) that exploit hardware duplication and combines it with the On-Chip Debug features existing in many processors. The new technique increases the observability of faults (thus increasing detection probability and reducing latency) and is characterized by a very reduced intrusiveness in terms of changes required in the application code.