Programmable restricted SEC codes to mask permanent faults in semiconductor memories

With increasing storage capacities, spare memory columns aimed at replacing defective regular columns remain generally available to repair malfunctioning storage cells. The existing repair methods are based on column replacement. Consequently, the number of single-bit hard errors induced by malfunctioning storage cells is linear with respect to the number of redundant columns. We propose restricted single-error correction (RSEC) codes to enable the correction of an exponential number of single-bit errors. The RSEC codes are characterized by programmable parity-check matrices which allow the correction of different sets of errors. Depending on the accessed memory bank or segment, these matrices can be generated out of the (built-in) test result bits which indicate the columns with defective storage cells. The resulting RSEC-based method improves the memory repair capacity with limited performance overhead. Memory protection schemes are proposed in which each redundant column is used either to store RSEC check-bits or to replace completely defective regular columns.