DocumentCode :
1860370
Title :
Configurable serial fault-tolerant link for communication in 3D integrated systems
Author :
Pasca, Vladimir ; Anghel, Lorena ; Rusu, Claudia ; Benabdenbi, Mounir
Author_Institution :
TIMA Lab., Grenoble, France
fYear :
2010
fDate :
5-7 July 2010
Firstpage :
115
Lastpage :
120
Abstract :
Three-dimensional (3D) Thru-Silicon-Via (TSV) integration is emerging as a key enabling technology for future high performance systems. The TSV manufacturing defect rates lead to significant interconnect yield loss. For intra-die and inter-die interconnects, techniques such as via widening, via spreading and spare via insertion have been successfully used to improve the yield. However, for high fault rates these solutions are less effective and lead to unacceptable overheads. In this paper, configurable serial fault tolerant links are proposed for inter-die communication in 3D integrated systems. For high TSV fault rates, serial data transmission and signal remapping on fault-free wires are jointly used to ensure correct data transmission. After the interconnect tests, if faulty wires are detected then the link serializes data transmission such that only fault free wires are used. In the proposed link, any subset of data bits can be mapped on any subset of functional wires. Selecting a threshold serialization rate above which the link fails, enables optimal link designs that target interconnect technologies with high fault rates. The impact of inter-die configurable serial fault tolerant links on the performance and area overheads of 3D mesh networks-on-chip (3D NoC) is analyzed. The results show that for an 80% interconnect fault rate the latency degradation up to 14% and area overheads go up to 30%.
Keywords :
fault tolerance; integrated circuit interconnections; network-on-chip; 3D integrated systems; 3D mesh networks-on-chip; 3D thru-silicon-via integration; TSV manufacturing defect rates; configurable serial fault-tolerant link; fault-free wires; high TSV fault rates; high performance systems; inter-die communication; inter-die interconnects; interconnect yield loss; intra-die interconnects; optimal link design; serial data transmission; signal remapping; Clocks; Data communication; Fault tolerance; Fault tolerant systems; Switches; Three dimensional displays; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
On-Line Testing Symposium (IOLTS), 2010 IEEE 16th International
Conference_Location :
Corfu
Print_ISBN :
978-1-4244-7724-1
Type :
conf
DOI :
10.1109/IOLTS.2010.5560225
Filename :
5560225
Link To Document :
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