Phase noise and jitter in digital electronic components

We tested a few digital integrated circuits of different technology and families with the ultimate target of understanding low phase noise frequency synthesis. Digital electronics is appealing for its simplicity, reproducibility and cost, in applications where the lower noise of analog circuits is not mandatory. Our work is partially driven by the attempt of reducing the phase noise in two ways. First, by paralleling numerous gates, as in microwave and RF amplifiers. Secondly, to de-alias the output as we did in the Λ divider [1], yet with the largest pipeline made possible by the high toggling frequency of the newest FPGAs (≈1 GHz).