Title :
An analog VLSI multilayer perceptron and its application towards built-in self-test in analog circuits
Author :
Maliuk, Dzmitry ; Stratigopoulos, Haralampos -G ; Makris, Yiorgos
Author_Institution :
Electr. Eng. Dept., Yale Univ., New Haven, CT, USA
Abstract :
A proof-of-concept hardware neural network for the purpose of analog built-in self-test is presented. The network is reconfigurable into any one-hidden-layer topology within the constraints of the number of inputs and neurons. Analog operation domain of synapses and neurons in conjunction with the digital weight storage allow fast computational time, low power consumption and fast training cycle. The network is trained in the chip-in-the-loop fashion with the simulated annealing-based parallel weight perturbation training algorithm. Its effectiveness in learning how to separate nominal from faulty circuits is investigated on two case studies: a Butterworth filter and an operational amplifier. The results are compared to those of the software neural networks of equivalent topologies and limitations concerning the practical applicability are discussed.
Keywords :
Butterworth filters; VLSI; analogue integrated circuits; built-in self test; integrated circuit reliability; integrated circuit testing; multilayer perceptrons; neural chips; operational amplifiers; simulated annealing; Butterworth filter; analog VLSI multilayer perceptron; analog built-in self-test; analog circuits; chip-in-the-loop fashion; digital weight storage; faulty circuits; low power consumption; one-hidden-layer topology; operational amplifier; parallel weight perturbation training algorithm; proof-of-concept hardware neural network; simulated annealing; software neural networks; Artificial neural networks; Built-in self-test; Hardware; Neurons; Software; System-on-a-chip; Training;
Conference_Titel :
On-Line Testing Symposium (IOLTS), 2010 IEEE 16th International
Conference_Location :
Corfu
Print_ISBN :
978-1-4244-7724-1
DOI :
10.1109/IOLTS.2010.5560230
