A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS

Author

Lin, Ying-Zu ; Liu, Chun-Cheng ; Huang, Guan-Ying ; Shyu, Ya-Ting ; Chang, Soon-Jyh

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

2010

fDate

16-18 June 2010

Firstpage

243

Lastpage

244

Abstract

This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. The flash ADC controls thermometer MSBs of the DAC and SAR ADC controls the binary LSBs. The segmented DAC improves DNL during MSB transitions. The merged switching of MSB capacitors enhances operation speed. The 9-bit 150-MS/s ADC consumes 1.53 mW from a 1.2-V supply. The ENOB is 8.69 bit and ERBW is 100 MHz. The FOMs at 1.2 V, 150 MS/s and 1 V, 100 MS/s are 24.7 and 17.7 fJ/conversion-step, respectively. At 1.3-V supply voltage, the sampling rate achieves 200 MS/s.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; 3.5-bit flash coarse ADC; 6-bit SAR fine ADC; CMOS; MSB capacitors; binary LSB; differential segmented capacitive DAC; flash ADC controls; frequency 100 MHz; power 1.53 mW; size 90 nm; subranged SAR ADC; thermometer MSB; voltage 1.2 V; voltage 1.3 V; Accuracy; Capacitance; Capacitors; Frequency measurement; Linearity; Preamplifiers; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2010 IEEE Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-5454-9

Type

conf

DOI

10.1109/VLSIC.2010.5560246

Filename

5560246