Title :
A novel message switch for highly parallel systems
Author :
Wang, Shiwei ; Hsu, Yi-Wen ; Tan, C.J.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
A novel VLSI message switch design for application in highly parallel architectures is presented. The prominent features of this design are message combining, a shared central queue structure with a dynamic boundary and nonpreemptive priority, and a look-ahead protocol between switch nodes in adjacent stages. These features alleviate memory contention and increase the effective network bandwidth
Keywords :
VLSI; multiprocessor interconnection networks; parallel processing; protocols; VLSI; dynamic boundary; highly parallel architectures; highly parallel systems; look-ahead protocol; memory contention; message combining; message switch; network bandwidth; nonpreemptive priority; shared central queue structure; Availability; Bandwidth; CMOS technology; Hardware; Multiprocessor interconnection networks; Parallel architectures; Protocols; Switches; Telecommunication traffic; Traffic control;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63346
