A passive delta-sigma modulator for low-power applications

This paper demonstrates at the transistor level that sigma-delta modulators using passive filters can be good candidates for low power applications. The circuit we propose is composed of a latch-type self-timed comparator, a switched capacitor passive filter and a voltage reference with an additive dithering signal. Time-domain simulations show that 10-bit resolutions can be expected with usual over-sampling ratio values. The enhancement provided by dither noise is highlighted. The global current consumption is below 10 μA for a 1 MHz sampling frequency.