A low noise image rejection down CMOS mixer

Author

Phan, Anh-Tuan ; Kim, Chang-Wan ; Cha, Choong-Yul ; Kang, Min-Suk ; Lee, Sang-Gug ; Su, Chun-Deok ; Kim, Hoon-Tae

Author_Institution

RFME Lab., Inf. & Commun. Univ., Daejeon, South Korea

Volume

3

fYear

2004

fDate

25-28 July 2004

Abstract

This paper represents a low noise image rejection mixer in heterodyne architecture for 2 GHz applications based on 0.18 μm CMOS technology. The designed mixer uses series inductor and capacitors as a notch filter to suppress the image signal and parasitic capacitance to improve the noise figure (NF) and conversion gain. An image rejection of 20-60 dB is obtained in a 200 MHz of bandwidth around 2 GHz with IF varying from 100 to 300 MHz. The simulation results show single-side band (SSB) NF improved 4 dB, the voltage conversion gain of 14.4 dB, improved by more than 4 dB. The circuit operates at the supply voltage of 1.8 V, and dissipates 11.34 mW.

Keywords

CMOS integrated circuits; UHF mixers; capacitors; inductors; integrated circuit noise; notch filters; 0.18 micron; 1.8 V; 100 to 300 MHz; 11.34 mW; 14.4 dB; 2 GHz; 20 to 60 dB; 200 GHz; 4 dB; CMOS mixer; CMOS technology; circuit simulation; heterodyne architecture; low noise image rejection mixer; notch filter; parasitic capacitance; series capacitors; series inductor; single side band noise figure; CMOS technology; Capacitors; Filters; Image converters; Inductors; Noise figure; Noise measurement; Parasitic capacitance; Signal design; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on

Print_ISBN

0-7803-8346-X

Type

conf

DOI

10.1109/MWSCAS.2004.1354361

Filename

1354361