DocumentCode
1861328
Title
A new pulsewidth control loop for high-speed VLSI systems
Author
Lin, Steven Yung-Sheng ; Tu, Steve Hung-Lung
Author_Institution
Dept. of Electron. Eng., Fu Jen Catholic Univ., Taipei, Taiwan
Volume
3
fYear
2004
fDate
25-28 July 2004
Abstract
In this paper, we propose a new mechanism for high-speed pulsewidth control loop (PWCL), which a cascade control stage and a differential feedback control voltage are employed to adjust the input signal pulsewidth more efficiently. The detailed comparisons in terms of duty cycle, rising/falling time of the input signal has also been made. The verification of the approach has been performed with HSPICE simulation.
Keywords
SPICE; VLSI; cascade control; circuit feedback; circuit simulation; high-speed integrated circuits; HSPICE simulation; cascade control; differential feedback control voltage; high speed VLSI systems; high speed pulsewidth control loop; Charge pumps; Circuit simulation; Clocks; Control systems; Feedback circuits; Feedback control; Pulse circuits; Space vector pulse width modulation; Very large scale integration; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on
Print_ISBN
0-7803-8346-X
Type
conf
DOI
10.1109/MWSCAS.2004.1354363
Filename
1354363
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