A FPGA-based ROHC decompressor design

The bandwidth of the wireless channel is the most valuable resources in the whole wireless communication system. In order to utilize the limited wireless resources efficiently, the header´s overhead introduced by transmission protocols must be reduced by header compression. Robust Header Compression (ROHC) is a compression scheme aims at providing a compression scheme that has high compression efficiency and high robustness when used in wireless links. Previous studies of ROHC are mainly focused on the software implementation and optimization of key parameters. In this paper, we introduce the basic concept and technology of RHOC and give the architecture of RHOC hardware decompressor which works under U mode. The decompressor is implemented on FPGA. The design of the decompressor is present in this essay also. It can work effectively, and decompress the packet such as IR, IR-DYN and UO-0/UO-1/UO-2 correctly. The performance of ROHC hardware accelerator which includes compressor and decompressor is evaluated through simulation. The result shows that the ROHC hardware compressor can compress the 40 bytes IPV4/UDP/RTP packet to 3∼4 bytes, and decompress effectively by the decompressor.