DocumentCode
1861439
Title
Return path assumption validation for inductance modeling in digital design
Author
David, Lauréline ; Crégut, Corinne ; Huret, Fabrice ; Quéré, Yves ; Nyer, Frédéric
Author_Institution
STMicroelectronics, Crolles, France
fYear
2005
fDate
10-13 May 2005
Firstpage
93
Lastpage
96
Abstract
Inductance modeling for on-chip interconnects in a typical digital environment is proposed. Regarding the effective loop inductance computation, the issue of current return path assumptions is first discussed. Then, sensible assumptions about the return path localization are presented and systematically validated. Finally, representative structure models allowing pre-layout effective inductance estimations are suggested.
Keywords
digital circuits; inductance; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; digital design; inductance estimation; inductance modeling; loop inductance computation; on-chip interconnect; return path assumption validation; return path localization; Circuit noise; Circuit simulation; Delay effects; Delay estimation; Digital circuits; Frequency; Inductance; Integrated circuit interconnections; RLC circuits; Working environment noise;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Propagation on Interconnects, 2005. Proceedings. 9th IEEE Workshop on
Print_ISBN
0-7803-9054-7
Type
conf
DOI
10.1109/SPI.2005.1500909
Filename
1500909
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