DocumentCode
1861536
Title
Daily scheduling for R&D semiconductor fabrication
Author
Liao, Da-Yin ; Chang, Shi-Chung ; Yen, Shou-ren ; Chien, Cheng-chung
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
1993
fDate
2-6 May 1993
Firstpage
77
Abstract
The daily scheduling for a research and development (R&D) pilot line of semiconductor wafer fabrication is addressed. An integer programming problem formulation is given, which captures the salient features, such as high variety and very low volume, cyclic process flows, batching at diffusion machines, single mask for each photolithography operation, loop test, and engineering splitting and merging of wafer lots. A solution methodology for scheduling flow shops based on Lagrangian relaxation is extended to solve this class of problems. It may also effectively handle data inaccuracy and cope with production uncertainties. Numerical results demonstrate both the feasibility and potential of this method
Keywords
integer programming; integrated circuit manufacture; research and development management; scheduling; Lagrangian relaxation; R&D pilot line; R&D semiconductor fabrication; batching; cyclic process flows; daily scheduling; data inaccuracy; diffusion machines; high variety; integer programming; loop test; lot merging; lot splitting; photolithography; production uncertainties; semiconductor wafer fabrication; very low volume; Fabrication; Job shop scheduling; Lagrangian functions; Linear programming; Lithography; Merging; Production; Research and development; Testing; Uncertainty;
fLanguage
English
Publisher
ieee
Conference_Titel
Robotics and Automation, 1993. Proceedings., 1993 IEEE International Conference on
Conference_Location
Atlanta, GA
Print_ISBN
0-8186-3450-2
Type
conf
DOI
10.1109/ROBOT.1993.291868
Filename
291868
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