Title :
A 5Gb/s speculative DFE for 2x blind ADC-based receivers in 65-nm CMOS
Author :
Sarvari, Siamak ; Tahmoureszadeh, Tina ; Sheikholeslami, Ali ; Tamura, Hirotaka ; Kibune, Masaya
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Abstract :
This paper presents the design of a DFE for a 2x blind ADC-based RX. The DFE is implemented in 65-nm CMOS along with a 2x blind CDR and ADC. Our measured results confirm 5Gb/s data recovery with BER less than 10-12 with a channel introducing 13.3dB of attenuation at the Nyquist frequency of 2.5GHz. Without the DFE, the BER exceeds 10-8.
Keywords :
CMOS integrated circuits; analogue-digital conversion; decision feedback equalisers; error statistics; radio receivers; synchronisation; BER; CMOS integrated circuit; Nyquist frequency; bit rate 5 Gbit/s; blind ADC based receivers; blind clock recovery; blind data recovery; decision feedback equalizer; frequency 2.5 GHz; size 65 nm; Bit error rate; CMOS integrated circuits; Clocks; Decision feedback equalizers; Jitter; Probes; Receivers; ADC-based receiver; CMOS; blind sampling; speculative DFE;
Conference_Titel :
VLSI Circuits (VLSIC), 2010 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-5454-9
DOI :
10.1109/VLSIC.2010.5560273
