Title :
A 5Gb/s automatic sub-bit between-pair skew compensator for parallel data communications in 0.13µm CMOS
Author :
Zheng, Yuxiang ; Liu, Jin ; Payne, Robert ; Morgan, Mark ; Lee, Hoi
Author_Institution :
Univ. of Texas at Dallas, Richardson, TX, USA
Abstract :
A between-pair skew compensator for parallel data communications is presented. It can detect time skew between two independent data sequences using continuous-time correlations and then automatically align the two using a voltage controlled wide-bandwidth data delay line. A 5Gb/s sub-bit between-pair skew compensator in 0.13μm CMOS occupies 0.03mm2 active die area and dissipates 22.5mW.
Keywords :
CMOS integrated circuits; data communication; parallel processing; CMOS process; automatic sub-bit between-pair skew compensator; bit rate 5 Gbit/s; continuous-time correlation; data sequence; parallel data communication; power 22.5 mW; size 0.13 mum; time skew detection; voltage controlled wide-bandwidth data delay line; CMOS integrated circuits; Clocks; Data communication; Delay; Delay lines; Detectors; Logic gates;
Conference_Titel :
VLSI Circuits (VLSIC), 2010 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-5454-9
DOI :
10.1109/VLSIC.2010.5560278
