A 5Gb/s link with clock edge matching and embedded common mode clock for low power interfaces

A 5Gb/s signaling system was designed and fabricated in TSMC´s 40nm LP CMOS process. A new clock/data skew minimization technique with a source-synchronous transmit clock delay line and integrating receiver tolerates high frequency transmit clock jitter and supports rapid turn-on without the clock buffer latency of conventional source-synchronous systems. A second method to minimize clock distribution via embedded clocking with superposition of clock in the common-mode was also explored.