DocumentCode :
1861783
Title :
A 1.07 Tbit/s 128×128 swizzle network for SIMD processors
Author :
Satpathy, Sudhir ; Foo, Zhiyoong ; Giridhar, Bharan ; Dreslinski, Ronald ; Sylvester, Dennis ; Mudge, Trevor ; Blaauw, David
Author_Institution :
Univ. of Michigan, Ann Arbor, MI, USA
fYear :
2010
fDate :
16-18 June 2010
Firstpage :
81
Lastpage :
82
Abstract :
A novel circuit switched swizzle network called XRAM is presented. XRAM uses an SRAM-based approach producing a compact footprint that scales well with network dimensions while supporting all permutations and multicasts. Capable of storing multiple shuffle configurations and aided by a novel sense-amp for robust bit-line evaluation, a 128×128 XRAM fabricated in 65nm achieves a bandwidth exceeding 1Tbit/s, enabling a 64-lane SIMD engine operating at 0.72V to save 46.8% energy over an iso-throughput conventional 16-lane implementation at 1.1V.
Keywords :
SRAM chips; microprocessor chips; parallel processing; SIMD processors; SRAM based approach; XRAM; bit line evaluation; circuit switched swizzle network; multicasts; permutations; sense amp; shuffle configurations; Delay; Discharges; Encoding; Program processors; Programming; Random access memory; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits (VLSIC), 2010 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-5454-9
Type :
conf
DOI :
10.1109/VLSIC.2010.5560282
Filename :
5560282
Link To Document :
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