Title :
A zero-crossing based 12b 100MS/s pipelined ADC with decision boundary gap estimation calibration
Author :
Chu, Jack ; Brooks, Lane ; Lee, Hae-Seung
Author_Institution :
MIT, Cambridge, MA, USA
Abstract :
This paper describes a 12-bit zero-crossing based pipeline 100-MS/s ADC. The prototype ADC, fabricated in a 90-nm CMOS process, occupies 0.32 mm2. The capacitor mismatch is calibrated by decision boundary gap estimate algorithm that runs in the background. It achieves an ENOB of 10.2 bits for a 49 MHz input signal and dissipates 6.2 mW from a 1.2V supply for a FOM of 53fJ/step.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; pipeline arithmetic; CMOS process; capacitor mismatch; decision boundary gap estimation calibration; frequency 49 MHz; pipelined ADC; power 6.2 mW; size 90 nm; voltage 1.2 V; zero-crossing; Calibration; Capacitors; Charge transfer; Estimation; Histograms; Inverters; Voltage measurement;
Conference_Titel :
VLSI Circuits (VLSIC), 2010 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-5454-9
DOI :
10.1109/VLSIC.2010.5560285
