A new PSPICE sub-circuit for the power MOSFET featuring global temperature options

Author

Hepp, William J. ; Wheatley, C. Frank, Jr.

Author_Institution

Harris Semicond., Mountaintop, PA, USA

fYear

1991

fDate

24-27 Jun 1991

Firstpage

533

Lastpage

544

Abstract

An empirical sub-circuit implemented in PSPICE is presented. It accurately portrays the vertical DMOS power MOSFET electrical and thermal responses. Excellent agreement is demonstrated between measured and modeled responses, including first and third quadrant MOSFET and gate charge behavior, body diode effects, breakdown voltage at high and low currents, gate equivalent series resistance, and package inductances for temperatures between -55°C and 175°C. Parameter extraction is relatively straightforward, as described

Keywords

digital simulation; equivalent circuits; insulated gate field effect transistors; power transistors; -55 to 175 degC; PSPICE sub-circuit; body diode effects; breakdown voltage; electrical responses; empirical sub-circuit; gate charge behavior; gate equivalent series resistance; global temperature options; package inductances; parameter extraction; thermal responses; vertical DMOS power MOSFET; Charge measurement; Current measurement; Diodes; Electric resistance; Electrical resistance measurement; Immune system; MOSFET circuits; Packaging; Power MOSFET; SPICE;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Electronics Specialists Conference, 1991. PESC '91 Record., 22nd Annual IEEE

Conference_Location

Cambridge, MA

Print_ISBN

0-7803-0090-4

Type

conf

DOI

10.1109/PESC.1991.162726

Filename

162726