Title :
A 12 bit 1.6 GS/s BiCMOS 2×2 hierarchical time-interleaved pipeline ADC
Author :
El-Chammas, Manar ; Xiaopeng Li ; Kimura, Shunji ; Maclean, Kenneth ; Hu, Jiankun ; Weaver, Mark ; Gindlesperger, Matthew ; Kaylor, Scott ; Payne, Roger ; Sestok, Charles ; Bright, William
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
fDate :
Sept. 30 2013-Oct. 3 2013
Abstract :
A 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process is presented. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T/H to improve the dynamic performance of the individual sub-ADCs and to reduce both the complexity of the required interleaving background calibration algorithms and the error rate. It achieves an SFDR of 79 dBc at low frequency inputs and 66 dBc at Nyquist, and has an error rate of less than 10-9.
Keywords :
BiCMOS integrated circuits; Ge-Si alloys; analogue-digital conversion; pipeline processing; BiCMOS ADC; SiGe; analog-digital converter; complementary BiCMOS process; hierarchical time-interleaved pipeline ADC; interleaving background calibration algorithms; size 0.18 mum; BiCMOS integrated circuits; Calibration; Clocks; Linearity; Master-slave; Pipelines; Timing; pipeline A/D; time-interleaving; track-and-hold;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2013 IEEE
Conference_Location :
Bordeaux
Print_ISBN :
978-1-4799-0126-5
DOI :
10.1109/BCTM.2013.6798144
