• DocumentCode
    1862120
  • Title

    In-situ measurement of variability in 45-nm SOI embedded DRAM arrays

  • Author

    Agarwal, Kanak ; Hayes, Jerry ; Barth, John ; Jacunski, Mark ; Nowka, Kevin ; Kirihata, Toshiaki ; Iyer, Subramanian

  • Author_Institution
    IBM Res., Austin, TX, USA
  • fYear
    2010
  • fDate
    16-18 June 2010
  • Firstpage
    189
  • Lastpage
    190
  • Abstract
    A technique for in-situ measurement of process variation in deep trench capacitance, bitline capacitance, and device threshold voltage in embedded DRAM arrays is presented. The technique is used to directly measure the parameter statistics in two product representative 45-nm SOI eDRAM arrays.
  • Keywords
    DRAM chips; capacitance; silicon-on-insulator; SOI embedded DRAM arrays; bitline capacitance; deep trench capacitance; device threshold voltage; in-situ measurement; process variation; size 45 nm; Arrays; Capacitance; Capacitance measurement; Microprocessors; Random access memory; Voltage measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2010 IEEE Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-5454-9
  • Type

    conf

  • DOI
    10.1109/VLSIC.2010.5560302
  • Filename
    5560302
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1862120