Improvements in Capacitor Voltage Balancing using Multi-phase Diode-clamped Multi-level Inverters

The aim of this paper is to show that with three-level multi-phase inverter systems, the extra load connections involved in the inversion process reduce the amplitude and increase the frequency of voltage ripple across the DC link capacitors, assuming the same DC capacitance and the same total power output. Symmetrical Regular Sampled Phase Disposition PWM (SRSPDPWM) is employed to generate the PWM signals for the inverter using an Altera Cyclone FPGA. A 3-level 5-phase NPC inverter based on Power MOSFETs is used to compare the cyclic voltage variation of the 3-level 3-phase system with that of the 3-level 5-phase system.