DocumentCode
1862159
Title
Improvements in Capacitor Voltage Balancing using Multi-phase Diode-clamped Multi-level Inverters
Author
Liliang, Gao ; Fletcher, John E. ; Reay, Donald S. ; Libo, Zheng
Author_Institution
School of Engineering and Physical Sciences, Heriot-Watt University, Riccarton, Edinburgh, EH14, 4AS, UK. Email: lg31@hw.ac.uk
fYear
2006
fDate
4-6 April 2006
Firstpage
378
Lastpage
382
Abstract
The aim of this paper is to show that with three-level multi-phase inverter systems, the extra load connections involved in the inversion process reduce the amplitude and increase the frequency of voltage ripple across the DC link capacitors, assuming the same DC capacitance and the same total power output. Symmetrical Regular Sampled Phase Disposition PWM (SRSPDPWM) is employed to generate the PWM signals for the inverter using an Altera Cyclone FPGA. A 3-level 5-phase NPC inverter based on Power MOSFETs is used to compare the cyclic voltage variation of the 3-level 3-phase system with that of the 3-level 5-phase system.
Keywords
Multi-level Multi-phase; NPC Inverter; Voltage Imbalance;
fLanguage
English
Publisher
iet
Conference_Titel
Power Electronics, Machines and Drives, 2006. The 3rd IET International Conference on
Conference_Location
The Contarf Castle, Dublin, Ireland
Print_ISBN
0-86341-609-8
Type
conf
Filename
4123549
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