Title :
53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors
Author :
Mathew, Sanu ; Sheikh, Farhana ; Agarwal, Amit ; Kounavis, Mike ; Hsu, Steven ; Kaul, Himanshu ; Anders, Mark ; Krishnamurthy, Ram
Author_Institution :
Circuits Res. Lab., Intel Corp., Hillsboro, OR, USA
Abstract :
An on-die, reconfigurable AES encrypt/decrypt hardware accelerator is fabricated in 45nm CMOS, targeted for content-protection in high-performance microprocessors. Compared to conventional AES implementations, this design computes the entire AES round in native GF(24)2 composite-field with one-time GF(28)-to-GF(24)2 mapping cost amortized over multiple AES iterations. This approach along with a fused Mix/InvMixColumns circuit and folded ShiftRow datapath results in 20% area savings and 67% reduction in worst-case interconnect length, enabling AES-128/192/256 ECB block throughput of 53/44/38Gbps, 125mW power measured at 1.1V, 50°C.
Keywords :
CMOS integrated circuits; cryptography; microprocessor chips; CMOS; ECB block throughput; Mix/InvMixColumns circuit; composite field AES encrypt-decrypt accelerator; content protection; folded ShiftRow datapath; high performance microprocessors; recontigurable AES encrypt-decrypt hardware accelerator; Encryption; Hardware; Integrated circuit interconnections; Microprocessors; Polynomials; Throughput;
Conference_Titel :
VLSI Circuits (VLSIC), 2010 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-5454-9
DOI :
10.1109/VLSIC.2010.5560310
