Title :
A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip
Author :
Zhou, Dajiang ; Zhou, Jinjia ; He, Xun ; Kong, Ji ; Zhu, Jiayi ; Liu, Peilin ; Goto, Satoshi
Author_Institution :
Grad. Sch. of Inf., Production & Syst., Waseda Univ., Tokyo, Japan
Abstract :
An H.264/AVC HP video decoder is implemented in 90nm CMOS. Its maximum throughput reaches 4096×2160@60fps, which is at least 4.3× higher than the state-of-the-art. By using partial MB reordering and lossless frame recompression, 51% of DRAM bandwidth is reduced which results in 58% DRAM power saving. Meanwhile, various efficient parallelization techniques contribute to a core energy saving of 54%.
Keywords :
CMOS memory circuits; DRAM chips; data compression; digital signal processing chips; video coding; 4096×2160@60fps; CMOS; DRAM power saving; H.264/AVC high profile video decoder chip; lossless frame recompression; partial MB reordering; picture size 530 Mpixel; size 90 nm; Bandwidth; Decoding; Encoding; Pipelines; Random access memory; Streaming media; Throughput;
Conference_Titel :
VLSI Circuits (VLSIC), 2010 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-5454-9
DOI :
10.1109/VLSIC.2010.5560311
