Title :
A CMOS 6-Bit 16-GS/s time-interleaved ADC with digital background calibration
Author :
Huang, Chun-Cheng ; Wang, Chung-Yi ; Wu, Jieh-Tsorng
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
An 8-channel 6-bit 16-GS/s time-interleaved ADC was fabricated using a 65nm CMOS technology. Each A/D channel is a flash ADC using latch-type comparator with background offset calibration. Timing skews among the channels are also continuously calibrated in the background. The chip achieves 42.3dB SFDR and 30.8dB SNDR at 16 GS/s sampling rate.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; calibration; comparators (circuits); A/D channel; CMOS technology; CMOS time-interleaved ADC; SFDR; SNDR; background offset calibration; digital background calibration; flash ADC; latch-type comparator; size 65 nm; timing skews; Calibration; Clocks; Delay; Driver circuits; Latches; System-on-a-chip;
Conference_Titel :
VLSI Circuits (VLSIC), 2010 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-5454-9
DOI :
10.1109/VLSIC.2010.5560312
