DocumentCode
1862397
Title
A systematic methodology for designing multilevel systolic architectures
Author
Goutis, Costas E.
fYear
1993
fDate
3-6 May 1993
Firstpage
1738
Lastpage
1741
Keywords
Algorithm design and analysis; Computer architecture; Design methodology; Digital signal processing; Equations; Hardware; Iterative algorithms; Partitioning algorithms; Signal processing algorithms; Systolic arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
IEEE
Print_ISBN
0-7803-1281-3
Type
conf
Filename
693004
Link To Document