Title :
A 0.02mm2 65nm CMOS 30MHz BW all-digital differential VCO-based ADC with 64dB SNDR
Author :
Daniels, Jorg ; Dehaene, Wim ; Steyaert, Michiel ; Wiesbauer, Andreas
Author_Institution :
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium
Abstract :
A 300MHz all-digital differential VCO-based ADC occupies 0.02mm2 in 65nm CMOS, achieving a peak SFDR of 79dB and an SNDR of 64dB over a 30MHz BW. This high linearity is obtained using two VCOs in differential configuration in combination with an 11-points digital calibration. The power consumption is 11.4mW and the FOM is 150fJ/conv. step.
Keywords :
CMOS integrated circuits; analogue-digital conversion; voltage-controlled oscillators; 11-points digital calibration; CMOS; all-digital differential VCO-based ADC; differential configuration; frequency 300 MHz; size 65 nm; Bandwidth; CMOS integrated circuits; Calibration; Inverters; Linearity; Power demand; Voltage-controlled oscillators; VCO; all-digital; analog-to-digital conversion; differential; digital calibration; time-based quantizer;
Conference_Titel :
VLSI Circuits (VLSIC), 2010 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-5454-9
DOI :
10.1109/VLSIC.2010.5560314
