Title :
A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration
Author :
El-Chammas, Manar ; Murmann, Boris
Author_Institution :
Stanford Univ., Stanford, CA, USA
Abstract :
A 12-GS/s 5-bit time-interleaved flash ADC is realized in 65-nm CMOS. The design utilizes a background timing skew calibration technique to improve dynamic performance, and comparator offset calibration to reduce power dissipation. The experimental prototype achieves an SNDR of 25.1 dB at Nyquist and 27.5 dB for low frequency inputs. The circuit occupies an active area of 0.44 mm2 and consumes 81 mW from a 1.1-V supply.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; 5-bit time-interleaved flash ADC; CMOS; background timing skew calibration; power 81 mW; size 65 nm; voltage 1.1 V; CMOS integrated circuits; Calibration; Clocks; Converters; Power dissipation; Timing; Transistors; A/D conversion; calibration; time-interleaving;
Conference_Titel :
VLSI Circuits (VLSIC), 2010 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-5454-9
DOI :
10.1109/VLSIC.2010.5560315
