DocumentCode
1862523
Title
A 1.3-degree I/Q phase error, 7.1 – 8.7-GHz LO generator with single-stage digital tuning polyphase filter
Author
Kodama, Hiroshi ; Ishikawa, Hiromu ; Oshima, Naoki ; Tanaka, Akio
Author_Institution
NEC Corp., Kawasaki, Japan
fYear
2010
fDate
16-18 June 2010
Firstpage
145
Lastpage
146
Abstract
We have developed an LO generator having 1) a digitally I/Q imbalance tuning polyphase filter and 2) a PLL with a varactor-based VCO and an interleaved charge pump for wide frequency operation. A 90-nm CMOS implementation showed that the equivalent maximum phase error was below 1.3 degrees in 7.1 - 8.7-GHz frequency range.
Keywords
CMOS integrated circuits; phase locked loops; varactors; voltage-controlled oscillators; CMOS; I/Q phase error; LO generator; PLL; digitally I/Q imbalance tuning polyphase filter; frequency 7.18 GHz to 8.7 GHz; phase locked loops; single-stage digital tuning polyphase filter; size 90 nm; varactor; voltage-controlled oscillators; CMOS integrated circuits; Dynamic range; Generators; Phase locked loops; Tuning; Varactors; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2010 IEEE Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4244-5454-9
Type
conf
DOI
10.1109/VLSIC.2010.5560318
Filename
5560318
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