• DocumentCode
    1862564
  • Title

    All-digital CDR for high-density, high-speed I/O

  • Author

    Loh, Matthew ; Emami-Neyestanak, Azita

  • Author_Institution
    California Inst. of Technol., Pasadena, CA, USA
  • fYear
    2010
  • fDate
    16-18 June 2010
  • Firstpage
    147
  • Lastpage
    148
  • Abstract
    A novel all-digital CDR for source-synchronous links, and its implementation in 90nm CMOS, is presented. A phase alignment technique with ping-pong action between two clock phases is used. The system is implemented in static CMOS logic, occupies 0.234 mm2 and dissipates 16.6 mW at 6 Gb/s, demonstrating BER <;10-13 with PRBS-7 input. The compactness and all-static-CMOS nature of the system make it suitable for use in high-speed I/Os requiring per-pin synchronization.
  • Keywords
    CMOS logic circuits; clock and data recovery circuits; all-digital CDR; high-density high-speed I/O; per-pin synchronization; phase alignment; size 90 nm; source-synchronous links; static CMOS logic; CMOS integrated circuits; Calibration; Clocks; Delay; Delay lines; Generators; Multiplexing; CDR; all-digital; static CMOS;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2010 IEEE Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-5454-9
  • Type

    conf

  • DOI
    10.1109/VLSIC.2010.5560319
  • Filename
    5560319
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1862564