Title :
A 9.2–12GHz, 90nm digital fractional-N synthesizer with stochastic TDC calibration and −35/−41dBc integrated phase noise in the 5/2.5GHz bands
Author :
Ravi, A. ; Pellerano, S. ; Ornelas, C. ; Lakdawala, H. ; Tetzlaff, T. ; Degani, O. ; Sajadieh, M. ; Soumyanath, K.
Author_Institution :
Intel Labs., Intel Corp., Hillsboro, OR, USA
Abstract :
A 90nm CMOS, 9.2-12GHz digital fractional-N synthesizer for WLAN/WiMax is described. Stochastic calibration of time to digital conversion and a VCO phase noise minimization algorithm are used to achieve <;-35dBc integrated phase nose (100Hz to 10MHz), in the 5-6GHz band with spurs below -60dBc.
Keywords :
CMOS integrated circuits; WiMax; calibration; phase noise; voltage-controlled oscillators; wireless LAN; CMOS; VCO phase noise minimization; WLAN; WiMax; digital fractional-N synthesizer; frequency 9.2 GHz to 12 GHz; integrated phase noise; size 90 nm; stochastic TDC calibration; stochastic calibration; Calibration; Histograms; Minimization; Phase locked loops; Phase noise; Synthesizers; Voltage-controlled oscillators; 802.11n; 802.16e; TDC calibration; digital PLL; frequency synthesizer; phase noise minimization;
Conference_Titel :
VLSI Circuits (VLSIC), 2010 IEEE Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-5454-9
DOI :
10.1109/VLSIC.2010.5560321
