DocumentCode
1862662
Title
A 2.2GHz sub-sampling PLL with 0.16psrms jitter and −125dBc/Hz in-band phase noise at 700µW loop-components power
Author
Gao, Xiang ; Klumperink, Eric ; Socci, Gerard ; Bohsali, Mounir ; Nauta, Bram
Author_Institution
Univ. of Twente, Enschede, Netherlands
fYear
2010
fDate
16-18 June 2010
Firstpage
139
Lastpage
140
Abstract
A divider-less PLL exploits a phase detector that directly samples the VCO with a reference clock. No VCO sampling buffer is used while dummy samplers keep the VCO spur <;-56dBc. A modified inverter with low short-circuit current acts as a power efficient reference clock buffer. The 2.2 GHz PLL in 0.18 μm CMOS achieves -125dBc/Hz in-band phase noise with only 700 μW loop-components power.
Keywords
CMOS integrated circuits; buffer circuits; clocks; invertors; jitter; phase detectors; phase locked loops; phase noise; short-circuit currents; voltage-controlled oscillators; CMOS; VCO sampling buffer; dummy samplers; frequency 2.2 GHz; in-band phase noise; jitter; loop component; low short-circuit current; modified inverter; phase detector; power 700 muW; power efficient reference clock buffer; size 0.18 nm; subsampling PLL; Clocks; Inverters; Jitter; Phase locked loops; Phase noise; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2010 IEEE Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4244-5454-9
Type
conf
DOI
10.1109/VLSIC.2010.5560323
Filename
5560323
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