DocumentCode
1862682
Title
A high throughput systolic design for QR algorithm
Author
Jiann-Jenn Wang ; Chein-Wei Jen
Author_Institution
National Chiao Tung University
fYear
1993
fDate
3-6 May 1993
Firstpage
1742
Lastpage
1745
Keywords
Adaptive signal processing; Algorithm design and analysis; Computational complexity; Computer architecture; Delay; Parallel processing; Pipeline processing; Signal processing algorithms; Systolic arrays; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
IEEE
Print_ISBN
0-7803-1281-3
Type
conf
Filename
693005
Link To Document