A 4.8–6.8GHz phase-locked loop with power optimized design methodology for dividers

A 4.8-6.8GHz phase-locked loop (PLL) with a power optimized multi-modulus divider (MMD) for wireless and radar applications is presented in this paper. Based on the timing delay analysis and the self-oscillation frequency of the divider cells, the power consumption of the divide-by-two circuit (DTC) and divide-by-2/3 cells can be optimized, and thus minimum power consumption for divider chain can be achieved. To extend the frequency tuning range of the voltage controlled oscillator (VCO) without significant phase noise degradation, PMOS switches are used to reverse bias the parasitic diode. The proposed PLL achieves a measured tuning range of 34% and measured phase noise of -86dBc/Hz@10kHz offset and -114dBc/Hz@1MHz offset with a center frequency of 6.56GHz, and it consumes 64mW from a 2.0V supply voltage. The PLL system for a radar transceiver is implemented in a 0.13μm SiGe technology with a core area of 1.35×0.65mm².