DocumentCode
1862943
Title
100Gbit/s SiGe Clock and Data Recovery
Author
Beraud-Sudreau, Quentin ; Begueret, Jean-Baptiste ; Mazouffre, O. ; Pignol, Michel ; Baguena, Louis ; Neveu, Claude ; Deval, Yann ; Taris, T.
Author_Institution
IMS Lab., Univ. of Bordeaux, Bordeaux, France
fYear
2013
fDate
Sept. 30 2013-Oct. 3 2013
Firstpage
199
Lastpage
202
Abstract
Clock and data recovery (CDR) is the first logical block in serial data receiver and the latter performances depend on the CDR ones. In this paper, a 100 Gbit/s CDR designed in 130 nm BiCMOS SiGe process is presented. The CDR uses an Injection Locked Oscillator (ILO) and a feedback loop to lock the data and the clock in frequency and phase. The power consumption is 1.4 W under 2.3 V power supply.
Keywords
BiCMOS integrated circuits; Ge-Si alloys; circuit feedback; clock and data recovery circuits; injection locked oscillators; BiCMOS process; CDR; ILO; SiGe; bit rate 100 Gbit/s; clock and data recovery; feedback loop; injection locked oscillator; logical block; power 1.4 W; serial data receiver; size 130 nm; voltage 2.3 V; Band-pass filters; Clocks; Delays; Logic gates; Oscillators; Phase locked loops; Voltage control; CDR; ILO; Injection locked CDR; injection locked oscillator; phase comparator;
fLanguage
English
Publisher
ieee
Conference_Titel
Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2013 IEEE
Conference_Location
Bordeaux
ISSN
1088-9299
Print_ISBN
978-1-4799-0126-5
Type
conf
DOI
10.1109/BCTM.2013.6798175
Filename
6798175
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