• DocumentCode
    1863
  • Title

    Pipelined Radix- 2^{k} Feedforward FFT Architectures

  • Author

    Garrido, Mario ; Grajal, J. ; Sánchez, M.A. ; Gustafsson, Oscar

  • Author_Institution
    Dept. of Electr. Eng., Linkoping Univ., Linkoping, Sweden
  • Volume
    21
  • Issue
    1
  • fYear
    2013
  • fDate
    Jan. 2013
  • Firstpage
    23
  • Lastpage
    32
  • Abstract
    The appearance of radix-22 was a milestone in the design of pipelined FFT hardware architectures. Later, radix-22 was extended to radix-2k . However, radix-2k was only proposed for single-path delay feedback (SDF) architectures, but not for feedforward ones, also called multi-path delay commutator (MDC). This paper presents the radix-2k feedforward (MDC) FFT architectures. In feedforward architectures radix-2k can be used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which makes them suitable for the most demanding applications. Indeed, the proposed radix-2k feedforward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. As a result, the proposed radix-2k feedforward architectures not only offer an attractive solution for current applications, but also open up a new research line on feedforward structures.
  • Keywords
    circuit feedback; fast Fourier transforms; feedforward; pipeline arithmetic; DIF; DIT decomposition; MDC FFT architecture; MDF; SDF architecture; decimation in frequency; decimation in time decomposition; fast Fourier transform; feedforward structure; hardware resource; multipath delay commutator; multipath delay feedback; parallel feedback; pipelined FFT hardware architecture; pipelined radix-2k feedforward FFT architecture; single-path delay feedback; Clocks; Computer architecture; Delay; Feedforward neural networks; Indexes; Multiplexing; Throughput; Fast Fourier transform (FFT); VLSI; multipath delay commutator (MDC); pipelined architecture; radix-$2^{k}$ ;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2011.2178275
  • Filename
    6118316