• DocumentCode
    1863016
  • Title

    Multi-step word-line control technology in hierarchical cell architecture for scaled-down high-density SRAMs

  • Author

    Takeda, K. ; Saito, T. ; Asayama, S. ; Aimoto, Y. ; Kobatake, H. ; Ito, S. ; Takahashi, T. ; Takeuchi, K. ; Nomura, M. ; Hayashi, Y.

  • Author_Institution
    LSI Fundamental Res. Lab., NEC Electron. Corp., Sagamihara, Japan
  • fYear
    2010
  • fDate
    16-18 June 2010
  • Firstpage
    101
  • Lastpage
    102
  • Abstract
    A new hierarchical cell SRAM architecture, combined with a multi-step word-line control technology, has been developed to overcome rapid increase in random variability with no area-penalty. A 40nm-node 0.248 μm2-cell SRAM using a single power supply has been successfully fabricated, pushing up bit-density to 2.98Mb/mm2.
  • Keywords
    SRAM chips; hierarchical cell SRAM architecture; multistep word-line control; scaled-down high-density SRAM; Capacitance; Computer architecture; Delay; Driver circuits; Microprocessors; Power supplies; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2010 IEEE Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-5454-9
  • Type

    conf

  • DOI
    10.1109/VLSIC.2010.5560336
  • Filename
    5560336
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1863016