• DocumentCode
    1863196
  • Title

    A DPLL-based per core variable frequency clock generator for an eight-core POWER7™ microprocessor

  • Author

    Tierno, Jose ; Rylyakov, Alexander ; Friedman, Daniel ; Chen, Ann ; Ciesla, Anthony ; Diemoz, Timothy ; English, George ; Hui, David ; Jenkins, Keith ; Muench, Paul ; Rao, Gaurav ; Smith, George, III ; Sperling, Michael ; Stawiasz, Kevin

  • Author_Institution
    IBM Res., IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
  • fYear
    2010
  • fDate
    16-18 June 2010
  • Firstpage
    85
  • Lastpage
    86
  • Abstract
    A per-core clock generator for the eight-core POWER7™ processor is implemented with a digital PLL. This frequency generator is capable of smooth, controlled frequency slewing, minimizing the impact of di/dt. Frequency can be dynamically adjusted while the clock is running, and without skipping any cycles, thus enabling aggressive power management techniques.
  • Keywords
    digital phase locked loops; microprocessor chips; power aware computing; digital PLL; eight core POWER7™ microprocessor; frequency generator; per core variable frequency clock generator; power management techniques; Clocks; Frequency control; Frequency conversion; Generators; Phase frequency detector; Time frequency analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2010 IEEE Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-5454-9
  • Type

    conf

  • DOI
    10.1109/VLSIC.2010.5560342
  • Filename
    5560342
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1863196