Title :
Redundancy revisited [CMOS combinational circuits]
Author_Institution :
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
Abstract :
This paper shows that when it comes to CMOS designs undetectability does not necessarily imply redundancy. The definition of redundancy is extended to account for the special behavior encountered in CMOS designs. The accuracy of the new redundancy definition has been tested on several CMOS chips and has been found to be correct
Keywords :
CMOS logic circuits; combinational circuits; fault diagnosis; logic testing; redundancy; CMOS designs; combinational circuits; redundancy; stuck-at fault detectability; undetectability; Boolean functions; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Combinational circuits; Jacobian matrices; Logic design; Logic testing; Redundancy;
Conference_Titel :
Instrumentation and Measurement Technology Conference, 1998. IMTC/98. Conference Proceedings. IEEE
Conference_Location :
St. Paul, MN
Print_ISBN :
0-7803-4797-8
DOI :
10.1109/IMTC.1998.679819
