• DocumentCode
    1863221
  • Title

    Redundancy revisited [CMOS combinational circuits]

  • Author

    Savir, Jacob

  • Author_Institution
    Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
  • Volume
    1
  • fYear
    1998
  • fDate
    18-21 May 1998
  • Firstpage
    407
  • Abstract
    This paper shows that when it comes to CMOS designs undetectability does not necessarily imply redundancy. The definition of redundancy is extended to account for the special behavior encountered in CMOS designs. The accuracy of the new redundancy definition has been tested on several CMOS chips and has been found to be correct
  • Keywords
    CMOS logic circuits; combinational circuits; fault diagnosis; logic testing; redundancy; CMOS designs; combinational circuits; redundancy; stuck-at fault detectability; undetectability; Boolean functions; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Combinational circuits; Jacobian matrices; Logic design; Logic testing; Redundancy;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Instrumentation and Measurement Technology Conference, 1998. IMTC/98. Conference Proceedings. IEEE
  • Conference_Location
    St. Paul, MN
  • ISSN
    1091-5281
  • Print_ISBN
    0-7803-4797-8
  • Type

    conf

  • DOI
    10.1109/IMTC.1998.679819
  • Filename
    679819
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1863221