Title :
Partial scan: hardware and fault coverage trade-off
Author :
Greene, Bruce S. ; Mourad, Samiha ; El-Ziq, Jacob
Author_Institution :
Dept. of Electr. Eng., Santa Clara Univ., CA, USA
Abstract :
In this paper we present an efficient algorithm for the selection of flip-flops for partial scan design. The algorithm determines the vertex set to open loops of length K or higher. Applying the algorithm to several ISCAS-89 benchmarks yields the best results for large circuits. Our results consistently indicated it is sufficient to scan a smaller set of flip-flops than the MVFS without significant sacrifice in fault coverage. We have applied the algorithm to RTL benchmarks with promising results
Keywords :
automatic testing; circuit feedback; fault diagnosis; flip-flops; logic testing; sequential circuits; ISCAS-89 benchmarks; MVFS; RTL benchmarks; fault coverage; flip-flops; minimum feedback vertex set; partial scan design; Automatic testing; Benchmark testing; Circuit faults; Circuit testing; Feedback; Flip-flops; Hardware; Registers; Sequential analysis; Test pattern generators;
Conference_Titel :
Instrumentation and Measurement Technology Conference, 1998. IMTC/98. Conference Proceedings. IEEE
Conference_Location :
St. Paul, MN
Print_ISBN :
0-7803-4797-8
DOI :
10.1109/IMTC.1998.679822
