Title :
Modeling and Simulation of Multi-operation Microcode-Based Built-In Self Test for Memory Faults
Author :
Sharma, Ratnesh K. ; Sood, Aditi
Author_Institution :
Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Kurukshetra, India
Abstract :
As embedded memory area on-chip is increasing and memory density is growing, problem of faults is growing exponentially. This necessitates defining of novel test algorithms which can detect these new faults. March Tests belong to the newer line of testing algorithms which offer to detect these exponentially escalating faults. Most of these new March algorithms consist of as many as five or six operations per March element. This work presents an architecture which can implement these new March tests having number of operations per element according to the growing needs of embedded memory testing.
Keywords :
built-in self test; fault location; firmware; memory architecture; March algorithms; embedded memory area on-chip; embedded memory testing; exponentially escalating faults; fault detection; memory density; memory faults; multioperation microcode-based built-in self test modeling; multioperation microcode-based built-in self test simulation; test algorithms; Automatic testing; Built-in self-test; Clocks; Delay; Fault detection; Logic testing; Performance evaluation; Pulse generation; Signal processing; Size control; Built-In Self Test (BIST); Defect-Per Million (DPM); MUT (Memory Under Test); Memory Built-in Self Test (MBIST); Microcoded MBIST;
Conference_Titel :
Signal Acquisition and Processing, 2010. ICSAP '10. International Conference on
Conference_Location :
Bangalore
Print_ISBN :
978-1-4244-5724-3
Electronic_ISBN :
978-1-4244-5725-0
DOI :
10.1109/ICSAP.2010.61
