Architecture design for deblocking filter in H.264/JVT/AVC

This paper presents an efficient VLSI architecture for the deblocking filter in H.264/JVT/AVC. We use an array of 8×4 8-bit shift registers with reconfigurable data path to support both horizontal filtering and vertical filtering on the same circuit (a parallel-in parallel-out reconfigurable FIR filter). Two SRAM modules are carefully organized not only for the storage of current macroblock data and adjacent block data but also for the efficient access of pixels in different blocks. Simulation results show that under 0.25 μm technology, the synthesized logic gate count is only 19.1 K (not including a 96×32 SRAM and a 64×32 SRAM) when the maximum frequency is 100 MHz. Our architecture design can easily support real-time deblocking of 720p (1280×720) 30 Hz video. It is valuable for platform-based design of H.264 codec.