A novel VLSI architecture for multidimensional discrete wavelet transform

In this short paper we propose a novel VLSI architecture for multidimensional discrete wavelet transform (m-D DWT) based on systolic array and non-separable approach. The proposed architecture performs a decomposition of an N₁ × N₂ × ... × N_m image in about N₁ N₂...N_m/(2^m $1) clock cycles (ccs). This result considerably speeds up other known architectures. Besides, the advantages of the proposed architecture include very simple hardware complexity, regular data flow and low control complexity.