Enhanced Performance of H.264 Using FPGA Coprocessors in Video Surveillance

As video and image processing design challenges becoming more complex, FPGA based coprocessors are required to boost overall DSP performance. For a High Definition (HD) video compression standard like H.264/AVC, the computational performance required has outstripped what standalone DSPs can provide. This H.264/AVC standard achieves a significant improvement in coding efficiency at the cost of increased computational complexity and creates a big challenge for efficient hardware and software executions. This paper implements a novel design combining DSP hardware platform with FPGA coprocessor architecture for the H.264/AVC codec in video surveillance environments. The main motivation to go for the FPGA coprocessor approach was the scalability in terms of processing power, cycle count, and better control of logic implementation, high frame rates and enhancement to support HD resolution. A properly architected coprocessor system off-loads a DSP processor and efficiently executes computationally intensive blocks of H.264/AVC like motion estimation, motion compensation modules as part of hardware acceleration in FPGA freeing up more valuable processing power of the DSP system.