Bang-Bang CDR´s acquisition, locking, and jitter tolerance

Author

Chao He ; Kwasniewski, T.

Author_Institution

DOE, Carleton Univ., Ottawa, ON, Canada

fYear

2012

fDate

April 29 2012-May 2 2012

Firstpage

1

Lastpage

4

Abstract

The CDR (Clock and Data Recovery) using PLL with Bang-Bang PD (Phase Detector), CP (Charge Pump), and RC (Resistor and Capacitor) filter is widely used in Serdes circuits. This paper provides a detailed analysis to Bang-Bang CDR´s dynamic behaviors and jitter tolerance. Then the slewing conditions, locking condition, and jitter tolerance curve, which are verified by a model implemented in Simulink, are proposed for choosing the filter parameters when designing the circuits.

Keywords

capacitors; charge pump circuits; clock and data recovery circuits; filters; integrated circuit design; jitter; phase detectors; phase locked loops; resistors; Bang-Bang CDR acquisition; Bang-Bang CDR locking; Bang-Bang phase detector; PLL; Serdes circuit; Simulink; capacitor filter; charge pump; circuit design; clock and data recovery; jitter tolerance; resistor filter; slewing condition; Clocks; Detectors; Integrated circuit modeling; Jitter; Phase locked loops; Software packages; Voltage-controlled oscillators; CDR; integral path; jitter tolerance; proportional path; slewing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical & Computer Engineering (CCECE), 2012 25th IEEE Canadian Conference on

Conference_Location

Montreal, QC

ISSN

0840-7789

Print_ISBN

978-1-4673-1431-2

Electronic_ISBN

0840-7789

Type

conf

DOI

10.1109/CCECE.2012.6334824

Filename

6334824