Fault coverage improvement and test vector generation for combinational circuits using spectral analysis

This paper presents an algorithm for generating test vectors using static compaction. It employs spectral analysis to improve fault coverage and generate new test vectors based on the original ones. The technique can be used to improve fault coverage of RTL level vectors to detect gate level faults. Test generation, static compaction and fault coverage analysis are performed by using VHDL. The test generation algorithm generates a compact high fault coverage test vectors for combinational circuits described at different levels.