DocumentCode
1865647
Title
A DLL-based fractional-N frequency synthesizer with a programmable injection clock
Author
Haizheng Guo ; Kwasniewski, T.
Author_Institution
Carleton Univ., Ottawa, ON, Canada
fYear
2012
fDate
April 29 2012-May 2 2012
Firstpage
1
Lastpage
4
Abstract
A delay-locked loop (DLL) based fractional-N frequency synthesizer with a programmable injection clock is presented. The proposed DLL architecture overcomes the integer-N limitation of the conventional DLL-based frequency multiplier, and can achieve small frequency step while maintaining low jitter accumulation. The frequency multiplication part is achieved by using either edge-combing DLL or MDLL structure, while the programmable injection clock is obtained by employing a DLL-based digital-to-phase converter. Based on the proposed architecture, a frequency synthesizer with 50MHz-1.3GHz output frequency tuning range has been design in 0.18μm CMOS technology. And a multiplication ratio of MN / (N+k) can be obtained, in which M, N and K are programmable. The DLL achieves around -42dB reference spur level.
Keywords
CMOS integrated circuits; delay lock loops; frequency multipliers; frequency synthesizers; CMOS technology; DLL-based digital-to-phase converter; MDLL structure; delay-locked loop; edge-combing DLL; fractional-N frequency synthesizer; frequency 50 MHz to 1.3 GHz; frequency multiplication part; frequency multiplier; integer-N limitation; low jitter accumulation; multiplication ratio; programmable injection clock; size 0.18 micron; Clocks; Delay; Frequency synthesizers; Jitter; Multiplexing; Voltage control; delay-locked loop; digital-to-phase converter; fractional-N frequency synthesizer;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical & Computer Engineering (CCECE), 2012 25th IEEE Canadian Conference on
Conference_Location
Montreal, QC
ISSN
0840-7789
Print_ISBN
978-1-4673-1431-2
Electronic_ISBN
0840-7789
Type
conf
DOI
10.1109/CCECE.2012.6334833
Filename
6334833
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