Fermi level pinning at the polySi/metal oxide interface

Author

Hobbs, C. ; Fonseca, L. ; Dhandapani, V. ; Samavedam, S. ; Taylor, B. ; Grant, J. ; Dip, L. ; Triyoso, D. ; Hegde, R. ; Gilmer, D. ; Garcia, Raul ; Roan, D. ; Lovejoy, L. ; Rai, R. ; Hebert, L. ; Tseng, H. ; White, B. ; Tobin, P.

Author_Institution

Digital DNA Lab., APRDL, Austin, TX, USA

fYear

2003

fDate

10-12 June 2003

Firstpage

9

Lastpage

10

Abstract

We report here for the first time that Fermi pinning at the polySi/metal oxide interface causes high threshold voltages in MOSFET devices. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. This fundamental characteristic also affects the observed polySi depletion. Device data and simulation results will be presented.

Keywords

Fermi level; MOSFET; elemental semiconductors; hafnium compounds; semiconductor device models; silicon; Fermi level pinning; MOSFET; Si-HfO/sub 2/; Si-O-Al bonds; device simulation; interfacial Al/sub 2/O/sub 3/; polySi depletion; polySi/metal oxide interface; threshold voltages; Annealing; Artificial intelligence; CMOS process; DNA; Dielectrics; Hafnium oxide; Laboratories; MOCVD; MOS devices; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-033-X

Type

conf

DOI

10.1109/VLSIT.2003.1221060

Filename

1221060