Performance analysis of STC104 interconnection networks

Author

Lee, Hyo Jong ; Song, Byeong Yeol

Author_Institution

Dept. of Electron. Eng., Chonbuk Nat. Univ., Chonju, South Korea

fYear

1997

fDate

28 Apr-2 May 1997

Firstpage

56

Lastpage

60

Abstract

The fast routing chip, Inmos STC104 has been designed and is now available in the market. Many research results concerning the performance, design cost and scalability of the packet switch have been presented and are currently under evaluation. There is a great demand for an efficient and reliable router in high performance parallel processing systems or data management networks. The performance and characteristics of each different network topology (e.g. multistage networks, meshes, tori, and N-cubes) are vital to make a decision on an appropriate network. The paper reviews the technology utilized in the fast packet switch, STC104 and studies reliable routing algorithms for various network configurations. The performance of each different configuration is also studied and compared

Keywords

microprocessor chips; multiprocessor interconnection networks; packet switching; performance evaluation; Inmos STC104; N-cubes; STC104 interconnection networks; data management networks; design cost; fast routing chip; high performance parallel processing systems; meshes; multistage networks; network configurations; network topology; performance analysis; reliable router; reliable routing algorithms; tori; Costs; Multiprocessor interconnection networks; Network topology; Packet switching; Paper technology; Parallel processing; Performance analysis; Routing; Scalability; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

High Performance Computing on the Information Superhighway, 1997. HPC Asia '97

Conference_Location

Seoul

Print_ISBN

0-8186-7901-8

Type

conf

DOI

10.1109/HPC.1997.592122

Filename

592122