Title :
The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88 nm feature size and beyond
Author :
Kim, J.Y. ; Lee, C.S. ; Kim, S.E. ; Chung, I.B. ; Choi, Y.M. ; Park, B.J. ; Lee, Jae W. ; Kim, Dong In ; Hwang, Y.S. ; Hwang, D.S. ; Hwang, H.K. ; Park, J.M. ; Kim, D.H. ; Kang, N.J. ; Cho, M.H. ; Jeong, M.Y. ; Kim, H.J. ; Han, J.N. ; Kim, S.Y. ; Nam, B.Y
Author_Institution :
Adv. Technol. Dev., Samsung Electron. Co., Kyunggi-Do, South Korea
Abstract :
For the first time, 512 Mb DRAMs using a Recess-Channel-Array-Transistor(RCAT) are successfully developed with 88 nm feature size, which is the smallest feature size ever reported in DRAM technology with non-planar array transistor. The RCAT with gate length of 75 nm and recessed channel depth of 150 nm exhibits drastically improved electrical characteristics such as DIBL, BV/sub DS/, junction leakage and cell contact resistance, comparing to a conventional planar array transistor of the same gate length. The most powerful effect using the RCAT in DRAMs is a great improvement of data retention time. In addition, this technology will easily extend to sub-70 nm node by simply increasing recessed channel depth and keeping the same doping concentration of the substrate.
Keywords :
DRAM chips; contact resistance; electrical faults; insulated gate field effect transistors; 150 nm; 70 nm; 75 nm; 88 nm; DRAM technology; cell contact resistance; data retention time; doping concentration; electrical properties; gate length; junction leakage; nonplanar array transistor; recess channel array transistor; recessed channel depth; Capacitors; Computer aided engineering; Costs; Doping; Dry etching; Electric resistance; Random access memory; Research and development;
Conference_Titel :
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-033-X
DOI :
10.1109/VLSIT.2003.1221061